Stanford University and SLAC National Accelerator Laboratory led a team that has given superconducting quantum chips something classical computers have taken for granted for decades: working random-access memory. In a paper published in Nature Physics on 8 September 2026, the researchers report an eight-bit cascaded random-access quantum memory — RAQM for short — that a single processor qubit can address. Average access infidelity stayed less than 1.5% per mode. This is a laboratory memory module with classical addressing, not a finished fault-tolerant product and not the coherent “QRAM” architecture theorists sketch for oracle-style algorithms.
Why it matters
Every serious plan for useful quantum computers runs into a wiring and control problem. Today’s superconducting processors often treat every qubit like both a calculator and a filing cabinet. That forces control lines, calibration routines, and error-correction overhead to grow roughly with the number of qubits you want to keep alive. Classical machines escaped that trap by splitting the job: a small, fast processor and a large, addressable memory.
The Stanford–SLAC device is an experimental unit cell for that split in the quantum world. One nonlinear processor (a transmon) talks to a buffer layer; the buffer swaps quantum states in and out of a bank of long-lived cavity storage modes. The control resources of one logical qubit can, in this design, be multiplexed across many memory slots. If the idea scales, engineers get more logical capacity without a matching explosion in microwave lines — the kind of architectural win that decides whether error-corrected machines stay lab curiosities or become schedulable computers.
Strangers should care for the same reason they care about chip packaging and HBM stacks in AI: progress is not only smarter algorithms. It is also whether the hardware can store work without drowning in cables.
The numbers that pay the click
| Quantity | Value (Nature Physics / accompanying analysis) |
|---|---|
| Peg | Published 8 September 2026 |
| Memory size | Eight-bit cascaded RAQM |
| Addressing | One transmon → seven storage modes via a buffer |
| Average random-access infidelity | Less than 1.5% per mode |
| Isolated single-mode swap (raw / post-selected) | Average 99.32% / 99.71% fidelity across buffer–storage pairs |
| Size-7 random-read fidelities | About 98.74% to 98.89% per mode |
| Size-7 full-cycle infidelity per mode | 16.27% (paper: under ~17% surface-code depolarization threshold) |
| Best cited storage T1 in device table | Above 1.2 ms (Storage 2 reported at 1,254.8 µs) |
| Institutions | Stanford, SLAC, Fermilab, University of Chicago, NYU, Rutgers |
Those figures come from the peer-reviewed paper and its detailed device appendices, not from a press-conference gloss. The “less than 1.5%” line is the headline fidelity for arbitrary random access across the module. The cleaner ~0.5%-class single-mode swap numbers appear when a storage cell is exercised in isolation. Once seven storage modes share the same buffer and cycle through read–gate–write traffic, crosstalk and idle errors show up — and the team measured them instead of hand-waving them away.
How they did it
The hardware is a 3D superconducting “flute” cavity stack. Storage modes sit in a high-coherence multimode cavity. A buffer cavity stands between those modes and the transmon processor so the memory bank does not inherit the processor’s strong nonlinearities. An RF-flux-modulated SQUID coupler turns on beam-splitter interactions that swap a chosen storage mode with the buffer on demand. Addressing is classical: the experiment picks which mode to swap, rather than requiring a fully coherent quantum address register.
Lead equal contributors Ziqian Li and Eesh Gupta, with senior author David I. Schuster (Stanford / SLAC), report universal control in the single-photon {|0⟩, |1⟩} subspace of the cavity modes. They benchmark individual buffer–storage swaps with randomized benchmarking, then escalate to multiplexed “RAM RB” across all storage cells. That second test is the one that matters for architecture: every mode must survive other modes being read and written.
The error budget is unusually honest for a quantum-hardware debut. Many-body cross-Kerr interactions — state-dependent frequency shifts when several modes are occupied — dominate once the module is busy. Spectator-access dephasing during other modes’ swaps, storage decay, and residual swap infidelity all appear in the ledger. The buffer layer keeps the worst Kerrs from flooding the storage bank, but it does not delete physics. The paper’s claim is not perfection; it is that a size-7 module still lands a full memory cycle under the depolarization threshold figure they use for surface-code comparison (~17%), with a calculated 16.27% per-mode infidelity after that cycle.
What this is not
It is not a shipping quantum server. It is not proof that a hundred logical qubits are one product cycle away. It is not Quantinuum’s trapped-ion logical-error work, not Google Willow’s reinforcement-learning calibration paper from earlier in 2026, and not the quantum LDPC packing story already live on The Good Signal. Those are different platforms and different claims.
It is also not coherent QRAM in the Giovannetti–Lloyd–Maccone sense. The authors are explicit: classical addressing swaps states between storage and processor. That is exactly what you want for a DRAM-like subsystem beside a logical processor grid — and a different object from an addressable oracle memory inside an algorithm.
What to watch
Three near-term tests will decide whether RAQM becomes a standard brick or a beautiful one-off.
First, coupler linearization. The team points to series-junction and balanced coupler designs that should suppress the buffer–storage Kerrs that dominate today’s error budget. If random-read fidelity can be pushed toward the 99.9% class they sketch in the outlook, the architecture’s control-line savings get much more persuasive.
Second, cavity coherence. Aluminum flute modes already reach millisecond T1 in places; niobium cavities with tens of milliseconds of photon lifetime would shrink idle decay and let memory size grow before error correction has to babysit every slot.
Third, integration with a real logical grid. The unit cell only matters when many RAQM modules sit beside a surface-code or bosonic logical processor and run refresh on a schedule. Transversal operations inside the memory module are advertised as a latency win; that has to be demonstrated with logical qubits, not only with physical Fock states.
For readers tracking the quantum race by a single phone-readable number, keep the pair that already cleared peer review: 8 memory bits under classical control, and access errors averaging under 1.5% per mode on the published device. Everything else — product timelines, “quantum advantage” slogans, investor decks — is downstream of whether those two numbers keep improving when the module is wired into a larger machine.
Sources
- Li, Z., Gupta, E., Zhao, F. et al. A cascaded random access quantum memory. Nature Physics (2026). Published 8 September 2026. https://doi.org/10.1038/s41567-026-03418-w
- Same work (open preprint HTML): https://arxiv.org/html/2503.13953 — arXiv:2503.13953
- Figshare data/code deposit cited by the paper: https://doi.org/10.6084/m9.figshare.32736012
