D-Wave Quantum and collaborators from the Quantum Circuits lineage published a peer-reviewed result in Nature on 5 August 2026 — An entangling gate for dual-rail erasure qubits (DOI 10.1038/s41586-026-10822-y; Nature 656, 47–53) — that closes a long-standing gap for dual-rail cavity qubits: a fast two-qubit gate that keeps the favorable error hierarchy intact. The Swap–Wait–Swap (SWS) controlled-Z (CZ) runs in about 500 ns, posts an erasure rate of 0.53(2)% per gate (~0.5%), and leaves residual Pauli errors below 0.1% after erasure detection (IRB 0.108(5)%; conservative QST bound 0.12(1)%). Bit-flips sit near 10⁻⁶ per gate. End-to-end Bell-state fidelity for a single CZ circuit, including SPAM and single-qubit gates, reaches 99.60(1)%.

This is a physical two-qubit gate on erasure-encoded cavity qubits — not a hardware surface-code logical qubit. Stim simulations in the paper project Λ ≈ 27 for their structured noise model versus Λ ≈ 14 for a 0.1% two-qubit depolarizing channel; those are sims with idealized assumptions, flagged as such by the authors.

Why it matters

Quantum error correction gets cheaper when most errors are the kind the code can see. An erasure is an error at a known place and time: the hardware flags that a qubit left the computational subspace (here, photon loss to vacuum). Codes can typically correct about twice as many erasures as silent Pauli flips at the same code distance, and the surface-code threshold for pure erasure noise sits near ~25% — far above the ~1% scale for depolarizing Pauli noise.

Dual-rail cavity qubits encode one logical bit in a single microwave photon shared across a pair of cavities. Loss of that photon is detectable leakage — an erasure — rather than a silent flip. Idle dual-rails already show erasures dominating phase flips, with bit-flips vanishingly rare. The missing piece, until this paper, was a two-qubit entangling gate that did not wreck that hierarchy.

For a stranger, the stake is simple: if you can entangle qubits without turning most errors into invisible Pauli noise, fault-tolerant machines may need fewer physical qubits for the same logical reliability. This paper shows the gate can keep erasures dominant. It does not yet show a working surface-code logical qubit on that hardware.

Key numbers

QuantityValue (Nature experiment)
Peg / venue5 Aug 2026; Nature 656, 47–53
GateSWS CZ, dual-rail cavity qubits
Gate duration~500 ns
Erasure per CZ0.53(2)% (~0.5%); control 0.400(4)%, target 0.096(4)%
Residual Pauli (post-erasure)<0.1%; IRB 0.108(5)%; conservative QST 0.12(1)%
Bit-flips per CZ~10⁻⁶ (control bit-flip fit 2.8(4)×10⁻⁶)
Single-CZ Bell fidelity (end-to-end)99.60(1)% (purity 99.46(3)%)
Stim Λ (structured SWS model)≈27
Stim Λ (0.1% depolarizing CZ)≈14
AffiliationD-Wave Quantum Inc. (New Haven); senior author Robert J. Schoelkopf (Yale / D-Wave)

Control–target asymmetry is real and expected: the control temporarily occupies a lossier transmon coupler, so its erasure and dephasing rates run roughly 3–4× higher than the target’s. The paper argues that asymmetry can be steered onto ancilla qubits in a surface-code layout.

How the gate works

Each dual-rail qubit is a pair of 3D microwave cavities holding one shared excitation. A middle SQUID transmon coupler links one cavity of the control rail to one cavity of the target. The SWS sequence has three steps:

  1. Swap — a parametric beamsplitter moves the control excitation into the coupler.
  2. Wait — the coupler’s strong dispersive shift on the target cavity (χbc/2π ≈ −1.51 MHz in the device) imprints a conditional phase for a wait near π/|χ|.
  3. Swap again — the excitation returns to the control cavity, completing a CZ in the dual-rail basis.

Because the gate preserves excitation number, photon loss — even in the coupler — leaves a detectable vacuum leakage rather than a hidden flip. No mode holds more than one photon, which also sidesteps cavity self-Kerr. If a qubit has already leaked to |00⟩ before the gate, the dispersive interaction never turns on and the partner sees identity; loss mid-gate maps to a bounded “CZ error” (conditional dephasing of unknown angle on the partner). That “leakage skips subsequent gates” behavior is why the team can delay erasure checks to the end of a syndrome round in their Stim models without wrecking distance scaling.

Plain language: most failures shout “I leaked,” so the decoder knows where to look. The leftover silent errors are mostly phase noise, not bit-flips — and they are rare enough that IRB puts them near one part in a thousand per gate.

What this is not

  • Not a hardware surface-code logical qubit. No below-threshold distance scaling was measured on chip. Λ ≈ 27 is from Stim under a simplified model (CZ errors only, perfect erasure checks, no single-qubit / measurement / idle noise). The paper states that adding those sources will reduce Λ. A fuller QEC treatment is flagged as “J.D.T., manuscript in preparation.”
  • Not the same story as IBM’s doped-Clifford sampling already on The Good Signal (certified hard sampling on a spacetime-coded superconducting processor). Different claim, different protocol.
  • Not the Innsbruck ion bounded-error simulation story. Different platform (ions vs dual-rail cavities), different milestone.
  • Not an end-user application. No chemistry molecule, no portfolio, no annealing-style optimization result. The output is a characterized CZ gate plus simulation evidence about structured noise.
  • Treat press “Λ = 10 roadmap” targets and commercial gate-model timelines as company framing, not as numbers measured in this Nature experiment.

Secondary coverage notes the research lineage predates D-Wave’s Quantum Circuits acquisition; the peer-reviewed affiliation is D-Wave, with Schoelkopf as corresponding senior author.

What to watch

  1. Companion QEC paper — whether realistic full-stack noise (imperfect erasure checks, SPAM, idling) still leaves Λ well above depolarizing baselines, and whether any hardware logical-qubit data appears.
  2. Deep-circuit stability — repeated Bell tomography shows roughly linear error out to ~15 CZs, then an unexplained near-quadratic drop in fidelity/purity out to N = 103; authors point to calibration drift or coupler-frequency fluctuations. Dynamical decoupling did not fix it.
  3. Integration scale — moving from a characterized two-qubit module to multi-qubit processors with yield, crosstalk, and real-time decoding; secondary reports cite D-Wave gate-model roadmap steps (e.g. DR17-class systems), which are separate from this paper’s measured device.
  4. Competing structured-noise bets — concurrent dual-rail work on tunable transmons (Huang et al., Nat. Phys. 2026) and cat-qubit bias approaches (AWS Ocelot / Alice & Bob) test the same strategic idea from different hardware.

The progress signal is a peer-reviewed CZ that keeps erasures easy to catch and Pauli leftovers small. The hedge stays in the lede: hierarchy preserved on the gate; logical-qubit proof still to come.

Sources